View 24LC16BSN_2964418.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

1998 microchip technology inc. ds20070h-page 1 features single supply with operation down to 2.5v low power cmos technology - 1 ma active current typical - 10 m a standby current typical at 5.5v -5 m a standby current typical at 3.0v organized as 8 blocks of 256 bytes (8 x 256 x 8) 2-wire serial interface bus, i 2 c ? compatible schmitt trigger inputs for noise suppression output slope control to eliminate ground bounce 100 khz (2.5v) and 400 khz (5v) compatibility self-timed write cycle (including auto-erase) page-write buffer for up to 16 bytes 2 ms typical write cycle time for page-write hardware write protect for entire memory can be operated as a serial rom factory programming (qtp) available esd protection > 4,000v 1,000,000 erase/write cycles guaranteed data retention > 200 years 8-pin dip, 8-lead or 14-lead soic packages available for extended temperature ranges description the microchip technology inc. 24lc16b is a 16k bit electrically erasable prom. the device is organized as eight blocks of 256 x 8 bit memory with a 2-wire serial interface. low voltage design permits operation down to 2.5 volts with standby and active currents of only 5 m a and 1 ma respectively. the 24lc16b also has a page-write capability for up to 16 bytes of data. the 24lc16b is available in the standard 8-pin dip and both 8-lead and 14-lead surface mount soic pack- ages. - commercial (c): 0 c to +70 c - industrial (i): -40 c to +85 c package types block diagram 24lc16b 24lc16b a0 a1 a2 v ss 1 2 3 4 8 7 6 5 v cc wp scl sda 24lc16b a0 a1 a2 v ss 1 2 3 4 8 7 6 5 v cc wp scl sda pdip soic nc a0 a1 nc 1 2 3 4 8 7 6 5 nc vcc wp nc a2 vss nc scl sda nc 14-lead soic hv generator eeprom array page latches ydec xdec sense amp r/w control memory control logic i/o control logic wp sda scl v cc v ss 24lc16b 16k 2.5v i 2 c serial eeprom i 2 c is a trademark of philips corporation. 20070hbook page 1 tuesday, july 7, 1998 12:00 pm
24lc16b ds20070h-page 2 1998 microchip technology inc. 1.0 electrical characteristics 1.1 maxim um ratings* v cc ...................................................................................7.0v all inputs and outputs w.r.t. v ss ................-0.3v to v cc +1.0v storage temperature ..................................... -65?c to +150?c ambient temp. with power applied................. -65?c to +125?c soldering temperature of leads (10 seconds) ............. +300?c esd protection on all pins ..................................................3 4 kv *notice: stresses above those listed under ?aximum ratings may cause permanent damage to the device. this is a stress rat- ing only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this speci?ation is not implied. exposure to maximum rating conditions for extended periods may affect device reliability. table 1-1: pin function table name function v ss ground sda serial address/data i/o scl serial clock wp write protect input v cc +2.5v to 5.5v power supply a0, a1, a2 no internal connection table 1-2: dc characteristics figure 1-1: bus timing start/stop vcc = +2.5v to +5.5v commercial (c): tamb = 0?c to +70?c industrial (i): tamb = -40?c to +85?c parameter symbol min max units conditions wp, scl and sda pins: high level input voltage v ih .7 v cc ? low level input voltage v il .3 v cc v hysteresis of schmitt trigger inputs v hys .05 v cc v (note) low level output voltage v ol .40 v i ol = 3.0 ma, v cc = 2.5v input leakage current i li -10 10 m av in = .1v to v cc output leakage current i lo -10 10 m av out = .1v to v cc pin capacitance (all inputs/outputs) c in , c out ?0pfv cc = 5.0v (note) tamb = 25?c, f clk = 1mhz operating current i cc write i cc read 3 1 ma ma v cc = 5.5v, scl = 400 khz standby current i ccs 30 100 m a m a v cc = 3.0v, sda = scl = v cc v cc = 5.5v, sda = scl = v cc wp = v ss note: this parameter is periodically sampled and not 100% tested. t su : sta t hd : sta v hys t su : sto start stop scl sda 20070hbook page 2 tuesday, july 7, 1998 12:00 pm
1998 microchip technology inc. ds20070h-page 3 24lc16b table 1-3: ac characteristics figure 1-2: bus timing data parameter symbol standard mode vcc = 4.5v - 5.5v fast mode units remarks min max min max clock frequency f clk 100 400 khz clock high time t high 4000 600 ns clock low time t low 4700 1300 ns sda and scl rise time t r 1000 300 ns (note 1) sda and scl fall time t f 300 300 ns (note 1) start condition hold time t hd : sta 4000 600 ns after this period the ?st clock pulse is generated start condition setup time t su : sta 4700 600 ns only relevant for repeated start condition data input hold time t hd : dat 0?ns data input setup time t su : dat 250 100 ns stop condition setup time t su : sto 4000 600 ns output valid from clock t aa 3500 900 ns (note 2) bus free time t buf 4700 1300 ns time the bus must be free before a new transmission can start output fall time from v ih min to v il max t of 250 20 +0.1 c b 250 ns (note 1), c b 100 pf input ?ter spike suppres- sion (sda and scl pins) t sp 50 50 ns (note 3) write cycle time t wr 10 10 ms byte or page mode endurance 1m 1m cycles 25 c, vcc = 5.0v, block mode (note 4) note 1: not 100% tested. c b = total capacitance of one bus line in pf. 2: as a transmitter, the device must provide an internal minimum delay time to bridge the unde?ed region (minimum 300 ns) of the falling edge of scl to avoid unintended generation of start or stop conditions. 3: the combined t sp and v hys speci?ations are due to new schmitt trigger inputs which provide improved noise and spike suppression. this eliminates the need for a t i speci?ation for standard operation. 4: this parameter is not tested but guaranteed by characterization. for endurance estimates in a speci? application, please consult the total endurance model which can be obtained on our website. t su : sta t f t low t high t r t hd : dat t su : dat t su : sto t hd : sta t buf t aa t aa t sp t hd : sta scl scl in scl out 20070hbook page 3 tuesday, july 7, 1998 12:00 pm
24lc16b ds20070h-page 4 1998 microchip technology inc. 2.0 functional description the 24lc16b supports a bi-directional 2-wire bus and data transmission protocol. a device that sends data onto the bus is de?ed as transmitter, and a device receiving data as receiver. the bus has to be controlled by a master device which generates the serial clock (scl), controls the bus access, and generates the start and stop conditions, while the 24lc16b works as slave. both, master and slave can operate as transmitter or receiver but the master device deter- mines which mode is activated. 3.0 bus characteristics the following bus protocol has been de?ed: data transfer may be initiated only when the bus is not busy. during data transfer, the data line must remain stable whenever the clock line is high. changes in the data line while the clock line is high will be interpreted as a start or stop condition. accordingly, the following bus conditions have been de?ed (figure 3-1). 3.1 bus not busy (a) both data and clock lines remain high. 3.2 star t data t ransf er (b) a high to low transition of the sda line while the clock (scl) is high determines a start condition. all commands must be preceded by a start condi- tion. 3.3 stop data t ransf er (c) a low to high transition of the sda line while the clock (scl) is high determines a stop condition. all operations must be ended with a stop condition. 3.4 data v alid (d) the state of the data line represents valid data when, after a start condition, the data line is stable for the duration of the high period of the clock signal. the data on the line must be changed during the low period of the clock signal. there is one clock pulse per bit of data. each data transfer is initiated with a start condition and terminated with a stop condition. the number of the data bytes transferred between the start and stop conditions is determined by the master device and is theoretically unlimited, although only the last six- teen will be stored when doing a write operation. when an overwrite does occur it will replace data in a ?st in ?st out fashion. 3.5 ac kno wledg e each receiving device, when addressed, is obliged to generate an acknowledge after the reception of each byte. the master device must generate an extra clock pulse which is associated with this acknowledge bit. the device that acknowledges, has to pull down the sda line during the acknowledge clock pulse in such a way that the sda line is stable low during the high period of the acknowledge related clock pulse. of course, setup and hold times must be taken into account. during reads, a master must signal an end of data to the slave by not generating an acknowledge bit on the last byte that has been clocked out of the slave. in this case, the slave (24lc16b) will leave the data line high to enable the master to generate the stop condition. note: the 24lc16b does not generate any acknowledge bits if an internal program- ming cycle is in progress. figure 3-1: data transfer sequence on the serial bus scl sda (a) (b) (d) (d) (a) (c) start condition address or acknowledge valid data allowed to change stop condition 20070hbook page 4 tuesday, july 7, 1998 12:00 pm
1998 microchip technology inc. ds20070h-page 5 24lc16b 3.6 de vice ad dressing a control byte is the ?st byte received following the start condition from the master device. the control byte consists of a four bit control code, for the 24lc16b this is set as 1010 binary for read and write operations. the next three bits of the control byte are the block select bits (b2, b1, b0). they are used by the master device to select which of the eight 256 word blocks of memory are to be accessed. these bits are in effect the three most signi?ant bits of the word address. it should be noted that the protocol limits the size of the memory to eight blocks of 256 words, therefore the pro- tocol can support only one 24lc16b per system. the last bit of the control byte de?es the operation to be performed. when set to one a read operation is selected, when set to zero a write operation is selected. following the start condition, the 24lc16b monitors the sda bus checking the device type identi?r being transmitted, upon a 1010 code the slave device outputs an acknowledge signal on the sda line. depending on the state of the r/w bit, the 24lc16b will select a read or write operation. figure 3-2: control byte allocation operation control code block select r/w read 1010 block address 1 write 1010 block address 0 slave address x = don? care 1010xxx r/w a start read/write 4.0 write operation 4.1 byte write following the start condition from the master, the device code (4 bits), the block address (3 bits), and the r/w bit which is a logic low is placed onto the bus by the master transmitter. this indicates to the addressed slave receiver that a byte with a word address will fol- low after it has generated an acknowledge bit during the ninth clock cycle. therefore the next byte transmit- ted by the master is the word address and will be writ- ten into the address pointer of the 24lc16b. after receiving another acknowledge signal from the 24lc16b the master device will transmit the data word to be written into the addressed memory location. the 24lc16b acknowledges again and the master gener- ates a stop condition. this initiates the internal write cycle, and during this time the 24lc16b will not gener- ate acknowledge signals (figure 4-1). 4.2 p a g e write the write control byte, word address and the ?st data byte are transmitted to the 24lc16b in the same way as in a byte write. but instead of generating a stop con- dition the master transmits up to 16 data bytes to the 24lc16b which are temporarily stored in the on-chip page buffer and will be written into the memory after the master has transmitted a stop condition. after the receipt of each word, the four lower order address pointer bits are internally incremented by one. the higher order seven bits of the word address remains constant. if the master should transmit more than 16 words prior to generating the stop condition, the address counter will roll over and the previously received data will be overwritten. as with the byte write operation, once the stop condition is received an inter- nal write cycle will begin (figure 4-2). figure 4-1: byte write figure 4-2: page write s p bus activity master sda line bus activity s t a r t s t o p control byte word address data a c k a c k a c k s p bus activity master sda line bus activity s t a r t control byte word address (n) data n data n + 15 s t o p a c k a c k a c k a c k a c k data n + 1 20070hbook page 5 tuesday, july 7, 1998 12:00 pm
24lc16b ds20070h-page 6 1998 microchip technology inc. 5.0 acknowledge polling since the device will not acknowledge during a write cycle, this can be used to determine when the cycle is complete (this feature can be used to maximize bus throughput). once the stop condition for a write com- mand has been issued from the master, the device ini- tiates the internally timed write cycle. ack polling can be initiated immediately. this involves the master send- ing a start condition followed by the control byte for a write command (r/w = 0). if the device is still busy with the write cycle, then no ack will be returned. if the cycle is complete, then the device will return the ack and the master can then proceed with the next read or write command. see figure 5-1 for ?w diagram. figure 5-1: acknowledge polling flow 6.0 write protection the 24lc16b can be used as a serial rom when the wp pin is connected to v cc . programming will be inhibited and the entire memory will be write-protected. send write command send stop condition to initiate write cycle send start send control byte with r/w = 0 did device acknowledge (ack = 0)? next operation no yes 7.0 read operation read operations are initiated in the same way as write operations with the exception that the r/w bit of the slave address is set to one. there are three basic types of read operations: current address read, random read, and sequential read. 7.1 current ad dress read the 24lc16b contains an address counter that main- tains the address of the last word accessed, internally incremented by one. therefore, if the previous access (either a read or write operation) was to address n, the next current address read operation would access data from address n + 1. upon receipt of the slave address with r/w bit set to one, the 24lc16b issues an acknowledge and transmits the eight bit data word. the master will not acknowledge the transfer but does gen- erate a stop condition and the 24lc16b discontinues transmission (figure 7-1). 7.2 random read random read operations allow the master to access any memory location in a random manner. to perform this type of read operation, ?st the word address must be set. this is done by sending the word address to the 24lc16b as part of a write operation. after the word address is sent, the master generates a start condition following the acknowledge. this terminates the write operation, but not before the internal address pointer is set. then the master issues the control byte again but with the r/w bit set to a one. the 24lc16b will then issue an acknowledge and transmits the 8-bit data word. the master will not acknowledge the transfer but does generate a stop condition and the 24lc16b dis- continues transmission (figure 7-2). 7.3 sequential read sequential reads are initiated in the same way as a ran- dom read except that after the 24lc16b transmits the ?st data byte, the master issues an acknowledge as opposed to a stop condition in a random read. this directs the 24lc16b to transmit the next sequentially addressed 8-bit word (figure 7-3). to provide sequential reads the 24lc16b contains an internal address pointer which is incremented by one at the completion of each operation. this address pointer allows the entire memory contents to be serially read during one operation. 7.4 noise pr otection the 24lc16b employs a v cc threshold detector circuit which disables the internal erase/write logic if the v cc is below 1.5 volts at nominal conditions. the scl and sda inputs have schmitt trigger and ?ter circuits which suppress noise spikes to assure proper device operation even on a noisy bus. 20070hbook page 6 tuesday, july 7, 1998 12:00 pm
1998 microchip technology inc. ds20070h-page 7 24lc16b figure 7-1: current address read figure 7-2: random read figure 7-3: sequential read sp bus activity master sda line bus activity s t a r t s t o p control byte data n a c k n o a c k s p s bus activity master sda line bus activity s t a r t s t o p control byte a c k word address (n) control byte s t a r t data (n) a c k a c k n o a c k p bus activity master sda line bus activity s t o p control byte a c k n o a c k data n data n + 1 data n + 2 data n + x a c k a c k a c k 8.0 pin descriptions 8.1 sd a serial ad dress/data input/ output this is a bi-directional pin used to transfer addresses and data into and data out of the device. it is an open drain terminal, therefore the sda bus requires a pullup resistor to v cc (typical 10k w for 100 khz, 2 k w for 400 khz). for normal data transfer sda is allowed to change only during scl low. changes during scl high are reserved for indicating the start and stop condi- tions. 8.2 scl serial cloc k this input is used to synchronize the data transfer from and to the device. 8.3 wp this pin must be connected to either v ss or v cc . if tied to vss normal memory operation is enabled (read/write the entire memory 000-7ff). if tied to v cc , write operations are inhibited. the entire memory will be write-protected. read operations are not affected. this feature allows the user to use the 24lc16b as a serial rom when wp is enabled (tied to v cc ). 8.4 a0, a1, a2 these pins are not used by the 24lc16b. they may be left ?ating or tied to either v ss or v cc . 20070hbook page 7 tuesday, july 7, 1998 12:00 pm
24lc16b ds20070h-page 8 1998 microchip technology inc. notes: 20070hbook page 8 tuesday, july 7, 1998 12:00 pm
1998 microchip technology inc. ds20070h-page 9 24lc16b notes: 20070hbook page 9 tuesday, july 7, 1998 12:00 pm
24lc16b ds20070h-page 10 1998 microchip technology inc. notes: 20070hbook page 10 tuesday, july 7, 1998 12:00 pm
24lc16b 24lc16b pr oduct identi cation system to order or to obtain information, e.g., on pricing or delivery, please use the listed part numbers, and refer to the factory o r the listed sales of?es. sales and suppor t data sheets products supported by a preliminary data sheet may have an errata sheet describing minor operational differences and recom- mended workarounds. to determine if an errata sheet exists for a particular device, please contact one of the following: 1. your local microchip sales of?e 2. the microchip corporate literature center u.s. fax: (602) 786-7277 3. the microchip worldwide web site (www.microchip.com) package: p = plastic dip (300 mil body), 8-lead sl = plastic soic (150 mil body), 14-lead sn = plastic soic (150 mil body), 8-lead temperature blank = 0 c to +70 c range: i = -40 c to +85 c device: 24lc16b 16k i 2 c serial eeprom 24lc16bt 16k i 2 c serial eeprom (tape and reel) 24lc16b - /p 1998 microchip technology inc. ds20070h-page 11 20070hbook page 11 tuesday, july 7, 1998 12:00 pm
information contained in this publication regarding device applications and the like is intended for suggestion only and may be superseded by updates. no representation or warranty is given and no liability is assumed by microchip t echnology incorporated with respect to the accuracy or use of such information, or infringement of patents or other intellectua l property rights arising from such use or otherwise. use of microchip s products as critical components in life support systems is not authorized except with express written approval by microchip. no licenses are conveyed, implicitly or other wise, under any intellectual property rights. the microchip logo and name are registered trademarks of microchip t echnology inc. in the u.s.a. and other countries. all rights reserved. all other trademarks mentioned herein are the property of their respective companies. 20070h-page 12 ? 1998 microchip technology inc. all rights reserved. ?1998, microchip technology incorporated, usa. 7/98 printed on recycled paper. m americas corporate of?e microchip technology inc. 2355 west chandler blvd. chandler, az 85224-6199 tel: 602-786-7200 fax: 602-786-7277 technical support: 602 786-7627 web: http://www.microchip.com atlanta microchip technology inc. 500 sugar mill road, suite 200b atlanta, ga 30350 tel: 770-640-0034 fax: 770-640-0307 boston microchip technology inc. 5 mount royal avenue marlborough, ma 01752 tel: 508-480-9990 fax: 508-480-8575 chicago microchip technology inc. 333 pierce road, suite 180 itasca, il 60143 tel: 630-285-0071 fax: 630-285-0075 dallas microchip technology inc. 14651 dallas parkway, suite 816 dallas, tx 75240-8809 tel: 972-991-7177 fax: 972-991-8588 dayton microchip technology inc. two prestige place, suite 150 miamisburg, oh 45342 tel: 937-291-1654 fax: 937-291-9175 detroit microchip technology inc. 42705 grand river, suite 201 novi, mi 48375-1727 tel: 248-374-1888 fax: 248-374-2878 los angeles microchip technology inc. 18201 von karman, suite 1090 irvine, ca 92612 tel: 714-263-1888 fax: 714-263-1338 new york microchip technology inc. 150 motor parkway, suite 202 hauppauge, ny 11788 tel: 516-273-5305 fax: 516-273-5335 san jose microchip technology inc. 2107 north first street, suite 590 san jose, ca 95131 tel: 408-436-7950 fax: 408-436-7955 americas (continued) toronto microchip technology inc. 5925 airport road, suite 200 mississauga, ontario l4v 1w1, canada tel: 905-405-6279 fax: 905-405-6253 asia/pacific hong kong microchip asia paci? rm 3801b, tower two metroplaza 223 hing fong road kwai fong, n.t., hong kong tel: 852-2-401-1200 fax: 852-2-401-3431 india microchip technology inc. india liaison of?e no. 6, legacy, convent road bangalore 560 025, india tel: 91-80-229-0061 fax: 91-80-229-0062 japan microchip technology intl. inc. benex s-1 6f 3-18-20, shinyokohama kohoku-ku, yokohama-shi kanagawa 222-0033 japan tel: 81-45-471- 6166 fax: 81-45-471-6122 korea microchip technology korea 168-1, youngbo bldg. 3 floor samsung-dong, kangnam-ku seoul, korea tel: 82-2-554-7200 fax: 82-2-558-5934 shanghai microchip technology rm 406 shanghai golden bridge bldg. 2077 yan?n road west, hong qiao district shanghai, prc 200335 tel: 86-21-6275-5700 fax: 86 21-6275-5060 asia/pacific (continued) singapore microchip technology singapore pte ltd. 200 middle road #07-02 prime centre singapore 188980 tel: 65-334-8870 fax: 65-334-8850 taiwan, r.o.c microchip technology taiwan 10f-1c 207 tung hua north road taipei, taiwan, roc tel: 886-2-2717-7175 fax: 886-2-2545-0139 europe united kingdom arizona microchip technology ltd. 505 eskdale road winnersh triangle wokingham berkshire, england rg41 5tu tel: 44-1189-21-5858 fax: 44-1189-21-5835 france arizona microchip technology sarl zone industrielle de la bonde 2 rue du buisson aux fraises 91300 massy, france tel: 33-1-69-53-63-20 fax: 33-1-69-30-90-79 germany arizona microchip technology gmbh gustav-heinemann-ring 125 d-81739 m?chen, germany tel: 49-89-627-144 0 fax: 49-89-627-144-44 italy arizona microchip technology srl centro direzionale colleoni palazzo taurus 1 v. le colleoni 1 20041 agrate brianza milan, italy tel: 39-39-6899939 fax: 39-39-6899883 6/11/98 w orldwide s ales and s ervice microchip received iso 9001 quality system certi?ation for its worldwide headquarters, design, and wafer fabrication facilities in january, 1997. our ?ld-programmable picmicro 8-bit mcus, serial eeproms, related specialty memory products and development systems conform to the stringent quality standards of the international standard organization (iso). 20070hbook page 12 tuesday, july 7, 1998 12:00 pm

▲Up To Search▲

Price & Availability of 24LC16BSN

	To Download 24LC16BSN Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .